1. Field of the Invention
The present invention relates to techniques for testing and debugging integrated circuits. More specifically, the present invention relates to a method and an apparatus that facilitate on-chip sampling of asynchronously triggered events.
2. Related Art
Advances in semiconductor process technology are making it possible for semiconductor devices to perform increasingly complicated functions at higher processing speeds. Consequently, the process of testing and debugging of integrated circuits is becoming more complicated.
Conventional testing schemes use automated testers to perform a test procedure on a chip and compare the output from the chip to a stored expected response. If an error occurs, designers will determine the root-cause of the error and systematically search for additional problems. Then, corrective action is taken, such as: fixing the design, iterating the chip development cycle, publishing errata, and/or adding additional features.
To find the root cause of an error, designers traditionally rely on a combination of existing techniques, such as: inference measurements, measurements using Built-In Self-Test (BIST) circuits, and/or external-probe measurements. Unfortunately, all of these techniques have limitations.
Inference measurements plot chip functionality versus power supply and frequency. For example, ‘shmoo’ plots reveal circuit behavior through power and frequency trends. FIG. 1 provides a drawing illustrating a shmoo plot (with voltage 110 plotted as a function of period 112) for an existing interference-measurement technique. This plot shows behavior that indicates an RC-dominated speedpath. In particular, as the period 112 decreases, the chip fails the test (as indicated by the gray-shaded squares) no matter how high the voltage 110 is raised. Unfortunately, interference measurements only probe the symptoms of a problem, i.e., they cannot directly measure specific circuits. Thus, while simple and fast, these measurements are of limited use in determining the root-cause of a problem.
BIST circuits generate inputs (often random) to specific logic blocks and check the resulting output signatures. FIG. 2 provides an illustration of a conventional BIST circuit. Based on instructions from BIST controller 210, pattern generator 212 provides inputs to logic block 214, and the resulting outputs are analyzed by signature checker 216. However, while BIST circuits have advantages (they are cheap, relatively non-invasive, and monitor the potential cause of failure), these circuits require chip area and use scan chains to handle inputs and outputs. Consequently, BIST circuits can generally only test digital logic states.
External probes (such as electron beams, mechanical probes, or laser probes) offer direct analog measurements of individual nodes. For example, FIG. 3 provides an illustration of an existing external-probe measurement technique in which the reflectivity of portions of a thinned chip 310 as a function of voltage is probed using a laser beam 312. Unfortunately, external probes require either invasive measurement techniques and/or test setups that are incompatible with packaged chips. Consequently, while external probes can be used to directly measure signals of interest, their expense and the required modifications to the circuits being probed can severely limit their use.
To supplement these techniques, designers have also used on-chip high-bandwidth analog samplers (so-called ‘analog BIST’ or analog probe circuits) that can probe specific nodes in a chip. These circuits are placed at nodes that are known to require post-fabrication probing or are opportunistically placed in critical circuits in case their fabricated performance misses specifications. During operation, analog probe circuits use well-known sub-sampling techniques to transfer high-bandwidth information off the chip for analysis. However, these circuits require a synchronous clock, and are, consequently, not suitable for measuring asynchronous signals.
Hence, what is needed is a method and an apparatus that facilitates on-chip testing and debugging of integrated circuits that support asynchronously triggered events (such as those associated with asynchronous signals) without the problems listed above.